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LP5521
www.ti.com
LED controller operation
mode (R,G,B_MODE)
00b
01b
10b
11b
Command
Wait
Ramp
Trigger
End
Set PWM
Other commands
SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
Table 16. LED controller operation
Power save condition
Disabled mode enables power save
Load program to SRAM mode prevents power save
Run program mode enables power save if there is no PWM activity and command
look-ahead filter condition is met
Direct control mode enables power save if there is no PWM activity
Power save condition
No PWM activity and current command wait time longer than 50 ms. If prescale = 1
then wait time needs to be longer than 80 ms.
Ramp Command PWM value reaches minimum 0 and current command execution
time left more than 50 ms. If prescale = 1 then time left needs to be more than 80 ms.
No PWM activity during wait for trigger command execution.
No PWM activity or Reset bit = 1
Enables power save if PWM set to 0 and next command generates at least 50 ms wait
No effect to power save
See application note "LP5521 Power Efficiency Considerations" for more information.
EXTERNAL CLOCK DETECTION
The presence of external clock can be detected by the LP5521. Program execution is clocked with internal 32
kHz clock or with external clock. Clocking is controlled with register address 08H bits, INT_CLK_EN and
CLK_DET_EN as seen on the following table.
External clock can be used if clock is present at CLK_32K pin. External clock frequency must be 32 kHz for the
program execution / PWM timing to be like specified. If higher or lower frequency is used, it will affect the
program engine execution speed. If other than 32kHz clock frequency is used, the program execution timings
must be scaled accordingly. The external clock detector block only detects too low clock frequency (<15 kHz). If
external clock frequency is higher than specified, the external clock detector notifies that external clock is
present. External clock status can be checked with read only bit EXT_CLK_USED in register address 0CH, when
the external clock detection is enabled (CLK_DET_EN bit = high). If EXT_CLK_USED = 1, then the external
clock is detected and it is used for timing, if automatic clock selection is enabled (see table below).
If external clock is stuck-at-zero or stuck-at-one, or the clock frequency is too low, the clock detector indicates
that external clock is not present.
If external clock is not used on the application, CLK_32K pin should be connected to GND to prevent floating of
this pin and extra current consumption.
Table 17. CONFIG register (08H):
Name
CLK_DET_EN,
INT_CLK_EN
Bit
1:0
Description
LED Controller clock source
00b = External clock source (CLK_32K)
01b = Internal clock
10b = Automatic selection
11b = Internal clock
LOGIC INTERFACE OPERATIONAL DESCRIPTION
LP5521 features a flexible logic interface for connecting to processor and peripheral devices. Communication is
done with I 2 C compatible interface and different logic input/output pins makes it possible to synchronize
operation of several devices.
Copyright ? 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP5521
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